Description: NCC Slovenia and EuroCC Czechia are inviting you to the workshop High-Level Synthesis for FPGA. Its aim is to demonstrate how to describe, debug, and implement application-specific accelerators on FPGA using the C/C++ language, rather than hardware description languages (e.g., VHDL or Verilog). Through simple examples, participants will learn how to write kernels that can be synthesized on FPGA fabric, transfer data between the host and an FPGA board, and employ various optimization techniques to make the design more efficient in terms of speed and resource utilization. Leveraging the capabilities of HLS, we will develop an accelerator for Cholesky matrix decomposition, utilizing the C/C++ programming language, along with the OpenCL and XRT libraries for development on AMD-Xilinx FPGAs. While the workshop primarily targets AMD-Xilinx FPGA boards, the principles and insights garnered can readily be applied to FPGAs from various other vendors.
Skills to be gained:
- Understanding the operation of heterogeneous computer systems with FPGA.
- Understanding the FPGA technology.
- Understanding the concepts of OpenCL and XRT software frameworks and HLS.
- How to write, translate, and run programs for FPGA.
- How to use HLS directives for design optimization.
Target audience: Researchers, engineers, students, and anyone interested in accelerating algorithm performance using FPGA technology.
Prerequisite knowledge: Programming language C/C++, usage of a SSH client.
Maximum number of participants: 15
Duration: 13.12.2023 - 14.12.2023, hours TBD
Location: University of Ljubljana, Faculty of computer and information science, Večna pot 113, Ljubljana Room: TBD
Virtual location: Zoom